Huawei HiSilicon Develops In-House RISC-V Core, Launches New AI Technology Framework MCU - In-Depth Analysis and Development Strategy Report on RISC-V Market
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According to China Securities Journal, Shanghai HiSilicon recently disclosed the A2 MCU focusing on industry-specific (Application Specific) and embedded AI technology (Artificial Intelligence).
HiSilicon stated that A2 is a new solution targeting home appliances, energy, industrial, and automotive sectors. It not only includes a series of RISC-V-based MCUs but also incorporates high-performance MPUs compatible with ARM instruction sets, along with tightly integrated and optimized operating systems.
The China Securities Journal pointed out that with national support, independent innovation in chip R&D has become an inevitable trend. The RISC-V open-source architecture has gained active industry practice and exploration, emerging as a global trend in chip innovation. Leveraging this flexible and open-source chip technology, China's domestic chip industry can compete with European and American chip companies on the same starting line, achieving overtaking in the chip industry. Industry experts indicate that RISC-V represents a significant opportunity for China's processor industry to achieve autonomy and control, with related companies expected to gain attention.
Regarding companies, according to Shanghai Securities News, A-share related concept stocks mainly include Feilixin and Dongruan Loadcom. 2023 marks the first year of high-performance, large-computing-power development for RISC-V, with many enterprises already joining the movement. Currently, there are numerous RISC-V core RTL codes available both domestically and internationally, many of which are open-source.
For example, Rocket Core, Boom Core, and LowRISC SoC all provide source code. For commercial use, there are also many companies offering stable RISC-V IP cores, such as SiFive and Microsemi abroad, and Alibaba's Pingtouge and Nuclei Technology domestically.
RISC-V Industry Development Status
RISC-V is an instruction set, not a processor implementation. An instruction set is a standard specification, akin to a common agreement. By adhering to the same standard, software and hardware produced by different manufacturers can work together seamlessly, much like standardized screw and nut dimensions.
With the instruction set standard in place, the most critical aspect is chip design. Based on the instruction set, microarchitecture design is completed, documented, and then transformed into source code through engineering development. Subsequently, EDA software is used to create the chip layout, which is then sent to foundries like TSMC or SMIC for fabrication.
In this process, microarchitecture design and implementation are crucial, representing the core competency of chip design. Once we possess the capability for microarchitecture design and implementation, we will no longer be constrained by the instruction set.
From a global distribution perspective, China, the United States, and Europe are advancing side by side. Chinese companies are highly engaged in this field. Among the RISC-V International Foundation's senior members, 14 are Chinese enterprises. Out of the 24 global board members, 9 are from China. Additionally, Chinese institutions and companies are actively participating as technical development partners.
History of RISC-V Development
Birth Period (1980s): The first-generation processor RISC-I was designed in 1980 under the Berkeley RISC project led by Professor Dave Patterson at UC Berkeley, laying the foundation for today's RISC architecture.
Subsequently, Professor Dave Patterson released the RISC-II prototype architecture in 1983, followed by the RISC-III architecture in 1984, and the RISC-IV architecture in 1988. The RISC design philosophy gave rise to a series of new architectures such as MIPS, the server-dominating IBM PowerPC, and ARM, which now rules the embedded market.
Exploration Period (2010): The RISC-V instruction set project began in 2010 at UC Berkeley and announced the complete open-sourcing of the ISA. Due to patent issues with Intel's X86 architecture instruction set and the expensive licensing of ARM architecture instruction sets.
Founding Professor Krste Asanovic's team decided to design a brand-new instruction set from scratch, and thus RISC-V was born! The 'V' here carries two meanings: first, it represents the fifth-generation instruction set architecture designed by Berkeley starting from RISC-I; second, it stands for variation and vectors.
Rapid Development Period (2015): In 2015, with the support of major industry alliances, the RISC-V Foundation was established. Its goal is to gather global innovative forces to jointly build an open and collaborative software and hardware community, create a RISC-V ecosystem, promote the broader adoption of the RISC-V instruction set, and further the evolution of future instruction set architectures. The industrial ecosystem is now entering a phase of rapid development. Currently, the foundation has over 327 members, including institutions, academics, and individual members.
In the current global chip market, the x86 and ARM instruction set architectures each dominate their respective fields. x86 has long been the leader in the general-purpose processor market, holding a monopoly in the PC and server sectors. Meanwhile, ARM has risen with the tide of mobile internet, becoming the most mainstream processor architecture for mobile devices.
RISC-V, with its advantages of being open-source, streamlined, and modular, is gaining traction among enterprises and is emerging as a new option for building computing ecosystems. Particularly in China, experts believe RISC-V can help break through Western restrictions in the chip sector, achieving self-reliance and leadership.
RISC-V's growth began in the IoT sector, and its future looks promising. As is well known, the RISC-V architecture is open, flexible, and modular, making it particularly suitable for the fragmented and diverse demands of the AIoT market.
The current chip computing architecture landscape is characterized by a "tripartite division" among x86, ARM, and RISC-V. x86 and ARM architectures account for over 95% of the market share, leaving most industry players to choose between the two. However, due to ARM's expensive licensing fees and the complexity of traditional x86 licensing, RISC-V—with its streamlined instructions, modularity, low cost, scalability, and ease of implementation—is becoming a new alternative for building computing ecosystems.
In the field of smart cockpits, RISC-V is a latecomer. Smart cockpits currently rely on Qualcomm's 64-bit processors, which already have a well-established ecosystem. Building a smart cockpit requires a robust ecosystem, which is currently a disadvantage for RISC-V in this domain.
However, RISC-V primarily expands virtualization support for cockpit systems, laying a foundation to become a rising star in future cockpit applications. Meanwhile, it now supports Java-based systems, and Google has announced Android's full compatibility with RISC-V.
Autonomous driving represents an ideal application scenario for RISC-V. For instance, it supports high-performance processing to deliver enhanced general computing power for self-driving vehicles. RISC-V's customizable instruction set extensions can accelerate specific applications. Additionally, it offers superior security isolation compared to competitors, with virtual partitioning being a major advantage.
In the post-Moore era, as chip manufacturing processes face bottlenecks, RISC-V's open-source instruction set has emerged as a game-changer, rewriting the rules of chip business models through the industry's cyclical "Tick-Tock" technological-commercial iterations.
Today, with ubiquitous connectivity becoming inevitable and computing scenarios growing increasingly complex, RISC-V's design philosophy of covering diverse computing scenarios perfectly aligns with contemporary demands. From both commercial and technical perspectives, RISC-V's entry into high-performance applications is now unavoidable.
As the IoT era dawns, RISC-V as a novel architecture possesses inherent advantages for deep integration in emerging fields like IoT. With its streamlined architecture, it may well establish absolute dominance in future IoT ecosystems.
With the development and maturation of technologies such as artificial intelligence, 5G, edge computing, and blockchain, traditional computing demands will face significant challenges, while new technological requirements will emerge. Domestic CPU companies stand to gain substantial opportunities if they can continuously expand their product portfolios during this period.
RISC-V is considered well-suited for the IoT market. The IoT market is more flexible and fragmented, with diverse customer needs. Currently, no single architecture dominates the market. RISC-V offers advantages such as low power consumption, cost-effectiveness, flexibility, scalability, and security. Although RISC-V itself is open-source and free, users can modify and sell their customized versions of the architecture.
Currently, the industry is optimistic about RISC-V's potential in high-performance applications. In scenarios like AI, PCs, data centers, smart cockpits, and smartphones, it is believed that mass-produced RISC-V chips will emerge within the next few years. The goal of RISC-V achieving a "one-third share of the market" is within reach.
The RISC-V industry research report aims to analyze future policy trends and regulatory developments from a national economic and industrial strategy perspective. It explores the market potential of the RISC-V industry, providing in-depth insights into key segments. The report offers a vivid depiction of market changes in terms of industry scale, structure, regional distribution, competition, and profitability, clarifying the direction for future development.